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?2013 integrated device technology, inc. february 2013 dsc-3089/08 1 features high-speed access and chip select times ? military: 20/25/35/45/55/70/90/120/150ns (max.) ? industrial: 20/25ns (max.) ? commercial: 15/20/25ns (max.) low-power consumption battery backup operation ? 2v data retention voltage (la version only) produced with advanced cmos high-performance technology cmos process virtually eliminates alpha particle soft-error rates input and output directly ttl-compatible static operation: no clocks or refresh required available in ceramic 24-pin dip, ceramic and plastic 24-pin thin dip and 24-pin soic military product compliant to mil-std-833, class b description the idt6116sa/la is a 16,384-bit high-speed static ram organized as 2k x 8. it is fabricated using high-performance, high-reliability cmos technology. access times as fast as 15ns are available. the circuit also offers a reduced power standby mode. when cs goes high, the circuit will automatically go to, and remain in, a standby power mode, as long as cs remains high. this capability provides significant system level power and cooling savings. the low-power (la) version also offers a battery backup data retention capability where the circuit typically consumes only 1w to 4w operating off a 2v battery. all inputs and outputs of the idt6116sa/la are ttl-compatible. fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. the idt6116sa/la is packaged in 24-pin 300mil plastic dip, 24-pin 600mil and 300mil ceramic dip, or 24-lead gull-wing soic providing high board-level packing densities. military grade product is manufactured in compliance to mil-std-883, class b, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. functional block diagram cs a 0 a 10 i/o 0 i/o 7 oe we 128 x 128 memory array i/o control address decoder input data circuit control circuit gnd 3089 drw 01 v cc , cmos static ram 16k (2k x 8-bit) idt6116sa idt6116la
2 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges pin configurations absolute maximum ratings (1) truth table (1) pin description capacitance (t a = +25c, f = 1.0 mh z ) dip/soic top view note: 1. this parameter is determined by device characterization, but is not production tested. symbol parameter (1) conditions max. unit c in input capacitance v in = 0v 8 pf c i/o i/o capacitance v out = 0v 8 pf 3089 tbl 03 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v cc +0.5v. symbol rating com'l. mil. unit v te rm (2) terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v t a operating temperature 0 to +70 -55 to +125 o c t bias temperature under bias -55 to +125 -65 to +135 o c t stg storage temperature -55 to +125 -65 to +150 o c p t power dissipation 1.0 1.0 w i out dc output current 50 50 ma 30 89 tb l 04 name description a 0 - a 10 address inputs i/o 0 - i/o 7 data input/output cs chip select we write enable oe output enable v cc power gnd ground 3089 tbl 01 note: 1. h = v ih , l = v il , x = don't care. mode cs oe we i/o standby h x x high-z read l l h data out read l h h high-z write l x l data in 30 89 tb l 02 3089 drw 02 5 6 7 8 9 10 11 12 gnd 1 2 3 4 24 23 22 21 20 19 18 17 p24-1 d24-2 d24-1 so24-2 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 v cc a 9 we a 10 i/o 5 i/o 4 oe 16 15 14 13 a 7 a 6 i/o 7 i/o 6 cs a 8 i/o 2 i/o 3
6.42 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges 3 notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc , only address inputs are cycling at f max, f = 0 means address inputs are not changing. dc electrical characteristics (1) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc - 0.2v) dc electrical characteristics (v cc = 5.0v 10%) recommended operating temperature and supply voltage recommended dc operating conditions notes: 1. v il (min.) = ?3.0v for pulse width less than 20ns, once per cycle. 2. v in must not exceed v cc +0.5v. grade ambient temperature gnd vcc military -55 o c to +125 o c0v 5.0v 10% industrial -40 o c to +85 o c0v 5.0v 10% commercial 0 o c to +70 o c0v 5.0v 10% 3089 tbl 05 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 (2) v gnd ground 0 0 0 v v ih input high voltage 2.2 3.5 v cc +0.5 v v il input low voltage -0.5 (1 ) ____ 0.8 v 30 89 tb l 06 symbol parameter test conditions idt6116sa idt6116la unit min. max. min. max. |i li | input leakage current v cc = max., v in = gnd to v cc mil. com'l & ind ____ ____ 10 5 ____ ____ 5 2 a |i lo | output leakage current v cc = max., cs = v ih , v out = gnd to v cc mil. com'l & ind ____ ____ 10 5 ____ ____ 5 2 a v ol output low voltage i ol = 8ma, v cc = min. ____ 0.4 ____ 0.4 v v oh output high voltage i oh = -4ma, v cc = min. 2.4 ____ 2.4 ____ v 3089 tbl 07 123symbol parameter power 6116sa15 6116sa20 6116la20 6116sa25 6116la25 unit com'l only com'l & ind mil com'l & ind mil i cc1 operating power supply current cs < v il , outputs open v cc = max., f = 0 sa 105 105 130 100 90 ma la _____ 95 120 95 85 i cc2 dynamic operating current cs < v il , outputs open v cc = max., f = f max (2) sa 150 130 150 120 135 ma la _____ 120 140 110 125 i sb standby power supply current (ttl level) cs > v ih , outputs open v cc = max., f = f max (2) sa 40 40 50 40 45 ma la _____ 35 45 35 40 i sb1 full standby power supply current (cmos level) cs > v hc , v cc = max., v in < v lc or v in > v hc , f = 0 sa 2 2 10 2 10 ma la _____ 0.1 0.9 0.1 0.9 3089 tbl 08
4 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges notes: 1. t a = + 25c 2. t rc = read cycle time. 3. this parameter is guaranteed by device characterization, but is not production tested. dc electrical characteristics (1) (continued) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc - 0.2v) notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc , only address inputs are toggling at f max , f = 0 means address inputs are not changing. data retention characteristics over all temperature ranges (la version only) (v lc = 0.2v, v hc = v cc ? 0.2v) typ. (1) v cc @ max. v cc @ symbol parameter test condition min. 2.0v 3.0v 2.0v 3.0v unit v dr v cc for data retention ____ 2.0 ____ ____ ____ ____ v i ccdr data retention current mil. com'l. ____ ____ 0.5 0.5 1.5 1.5 200 20 300 30 a t cdr (3) chip deselect to data retention time cs > v hc v in > v hc or < v lc ____ 0 ____ ____ ____ ns t r (3 ) operation recovery time t rc (2) ____ ____ ____ ____ ns i i li i input leakage current ____ ____ ____ 22 a 3089 tbl 10 l o b m y sr e t e m a r a pr e w o p 5 3 a s 6 1 1 6 5 3 a l 6 1 1 6 5 4 a s 6 1 1 6 5 4 a l 6 1 1 6 5 5 a s 6 1 1 6 5 5 a l 6 1 1 6 0 7 a s 6 1 1 6 0 7 a l 6 1 1 6 0 9 a s 6 1 1 6 0 9 a l 6 1 1 6 0 2 1 a s 6 1 1 6 0 2 1 a l 6 1 1 6 0 5 1 a s 6 1 1 6 0 5 1 a l 6 1 1 6 t i n u y l n o l i my l n o l i my l n o l i my l n o l i my l n o l i my l n o l i my l n o l i m i 1 c c y l p p u s r e w o p g n i t a r e p o , t n e r r u c s c < v l i , n e p o s t u p t u o v c c f , . x a m = = 0 a s0 90 90 90 90 90 90 9 a m a l5 85 85 85 85 85 85 8 i 2 c c g n i t a r e p o c i m a n y d , t n e r r u c s c < v l i , n e p o s t u p t u o v c c f = f , . x a m = x a m ) 2 ( a s5 1 10 0 10 0 10 0 10 0 10 0 10 9 a m a l5 0 15 90 90 95 85 85 8 i b s y l p p u s r e w o p y b d n a t s ) l e v e l l t t ( t n e r r u c s c > v h i n e p o s t u p t u o , v c c f = f , . x a m = x a m ) 2 ( a s5 35 25 25 25 25 25 2 a m a l0 30 20 20 25 25 15 1 i 1 b s r e w o p y b d n a t s l l u f s o m c ( t n e r r u c y l p p u s , ) l e v e l s c > v c h , v c c v , . x a m = n i < v c l v r o n i > v c h 0 = f , a s0 10 10 10 10 10 10 1 a m a l9 . 09 . 09 . 09 . 09 . 09 . 09 . 0 9 0 l b t 9 8 0 3
6.42 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges 5 low v cc data retention waveform ac test conditions data retention mode v cc cs t cdr 4.5v v dr 2v v dr 4.5v t r v ih v ih 3089 drw 03 , figure 2. ac test load (for t olz , t clz , t ohz , t whz , t chz & t ow ) figure 1. ac test load *including scope and jig. 3089 drw 04 30pf* 255 5v data out 480 , 5pf* 255 5v 480 data out 3089 drw 05 , input pulse levels input rise/fall times input timing reference levels output reference levels ac test load gnd to 3.0v 5ns 1.5v 1.5v see figures 1 and 2 3089 tbl 11
6 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges ac electrical characteristics (v cc = 5v 10%, all temperature ranges) (continued) notes: 1. 0c to +70c temperature range only. 2. ?55c to +125c temperature range only. 3. this parameter guaranteed with the ac load (figure 2) by device characterization, but is not production tested. ac electrical characteristics (v cc = 5v 10%, all temperature ranges) l o b m y sr e t e m a r a p 5 1 a s 6 1 1 6 ) 1 ( 0 2 a s 6 1 1 6 0 2 a l 6 1 1 6 5 2 a s 6 1 1 6 5 2 a l 6 1 1 6 5 3 a s 6 1 1 6 ) 2 ( 5 3 a l 6 1 1 6 ) 2 ( t i n u . n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m e l c y c d a e r t c r e m i t e l c y c d a e r5 1 _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 5 3 _ _ _ _ s n t a a e m i t s s e c c a s s e r d d a _ _ _ _ 5 1 _ _ _ _ 9 1 _ _ _ _ 5 2 _ _ _ _ 5 3s n t s c a e m i t s s e c c a t c e l e s p i h c _ _ _ _ 5 1 _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 5 3s n t z l c ) 3 ( z - w o l n i t u p t u o o t t c e l e s p i h c5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t e o d i l a v t u p t u o o t e l b a n e t u p t u o _ _ _ _ 0 1 _ _ _ _ 0 1 _ _ _ _ 3 1 _ _ _ _ 0 2s n t z l o ) 3 ( z - w o l n i t u p t u o o t e l b a n e t u p t u o0 _ _ _ _ 0 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t z h c ) 3 ( z - h g i h n i t u p t u o o t t c e l e s e d p i h c _ _ _ _ 0 1 _ _ _ _ 1 1 _ _ _ _ 2 1 _ _ _ _ 5 1s n t z h o ) 3 ( z - h g i h n i t u p t u o o t e l b a s i d t u p t u o _ _ _ _ 8 _ _ _ _ 8 _ _ _ _ 0 1 _ _ _ _ 3 1s n t h o e g n a h c s s e r d d a m o r f d l o h t u p t u o5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t u p ) 3 ( e m i t p u r e w o p o t t c e l e s p i h c0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t d p ) 3 ( e m i t n w o d r e w o p o t t c e l e s e d p i h c _ _ _ _ 5 1 _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 5 3s n 2 1 l b t 9 8 0 3 l o b m y sr e t e m a r a p 5 4 a s 6 1 1 6 ) 2 ( 5 4 a l 6 1 1 6 ) 2 ( 5 5 a s 6 1 1 6 ) 2 ( 5 5 a l 6 1 1 6 ) 2 ( 0 7 a s 6 1 1 6 ) 2 ( 0 7 a l 6 1 1 6 ) 2 ( 0 9 a s 6 1 1 6 ) 2 ( 0 9 a l 6 1 1 6 ) 2 ( 0 2 1 a s 6 1 1 6 ) 2 ( 0 2 1 a l 6 1 1 6 ) 2 ( 0 5 1 a s 6 1 1 6 ) 2 ( 0 5 1 a l 6 1 1 6 ) 2 ( t i n u . n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m e l c y c d a e r t c r e m i t e l c y c d a e r5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 9 _ _ _ _ 0 2 1 _ _ _ _ 0 5 1 _ _ _ _ s n t a a e m i t s s e c c a s s e r d d a _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 9 _ _ _ _ 0 2 1 _ _ _ _ 0 5 1s n t s c a e m i t s s e c c a t c e l e s p i h c _ _ _ _ 5 4 _ _ _ _ 0 5 _ _ _ _ 5 6 _ _ _ _ 0 9 _ _ _ _ 0 2 1 _ _ _ _ 0 5 1s n t z l c ) 3 ( z - w o l n i t u p t u o o t t c e l e s p i h c5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t e o d i l a v t u p t u o o t e l b a n e t u p t u o _ _ _ _ 5 2 _ _ _ _ 0 4 _ _ _ _ 0 5 _ _ _ _ 0 6 _ _ _ _ 0 8 _ _ _ _ 0 0 1s n t z l o ) 3 ( z - w o l n i t u p t u o o t e l b a n e t u p t u o5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t z h c ) 3 ( z - h g i h n i t u p t u o o t t c e l e s e d p i h c _ _ _ _ 0 2 _ _ _ _ 0 3 _ _ _ _ 5 3 _ _ _ _ 0 4 _ _ _ _ 0 4 _ _ _ _ 0 4s n t z h o ) 3 ( z - h g i h n i t u p t u o o t e l b a s i d t u p t u o _ _ _ _ 5 1 _ _ _ _ 0 3 _ _ _ _ 5 3 _ _ _ _ 0 4 _ _ _ _ 0 4 _ _ _ _ 0 4s n t h o e g n a h c s s e r d d a m o r f d l o h t u p t u o5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n 3 1 l b t 9 8 0 3
6.42 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges 7 timing waveform of read cycle no. 2 (1,2,4) timing waveform of read cycle no. 1 (1,3) timing waveform of read cycle no. 3 (1,3,4) notes: 1. we is high for read cycle. 2. device is continously selected, cs is low. 3. address valid prior to or coincident with cs transition low. 4. oe is low. 5. transition is measured 500mv from steady state. address oe cs t rc t aa t oe t acs data out t oh t olz (5) t clz (5) t ohz (5) t chz (5) 3089 drw 06 data valid t pd i cc i sb t pu v cc supply currents , address t rc t aa t oh t oh data out 3089 drw 07 previous data valid data valid , cs t acs data out t clz (5) t chz (5) data valid 3089 drw 08 ,
8 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges ac electrical characteristics (v cc = 5v 10%, all temperature ranges) notes: 1. 0c to +70c temperature range only. 2. ?55c to +125c temperature range only. 3. this parameter guaranteed with ac load (figure 2) by device characterization, but is not production tested. 4. the specification for t dh must be met by the device supplying write data to the ram under all operation conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . ac electrical characteristics (v cc = 5v 10%, all temperature ranges)(con't) 5 4 a s 6 1 1 6 ) 2 ( 5 4 a l 6 1 1 6 ) 2 ( 5 5 a s 6 1 1 6 ) 2 ( 5 5 a l 6 1 1 6 ) 2 ( 0 7 a s 6 1 1 6 ) 2 ( 0 7 a l 6 1 1 6 ) 2 ( 0 9 a s 6 1 1 6 ) 2 ( 0 9 a l 6 1 1 6 ) 2 ( 0 2 1 a s 6 1 1 6 ) 2 ( 0 2 1 a l 6 1 1 6 ) 2 ( 0 5 1 a s 6 1 1 6 ) 2 ( 0 5 1 a l 6 1 1 6 ) 2 ( l o b m y sr e t e m a r a p. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a mt i n u e l c y c e t i r w t c w e m i t e l c y c e t i r w5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 9 _ _ _ _ 0 2 1 _ _ _ _ 0 5 1 _ _ _ _ s n t w c e t i r w - f o - d n e o t t c e l e s p i h c0 3 _ _ _ _ 0 4 _ _ _ _ 0 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 9 _ _ _ _ s n t w a e t i r w - f o - d n e o t d i l a v s s e r d d a0 3 _ _ _ _ 5 4 _ _ _ _ 5 6 _ _ _ _ 0 8 _ _ _ _ 5 0 1 _ _ _ _ 0 2 1 _ _ _ _ s n t s a e m i t p u - t e s s s e r d d a0 _ _ _ _ 5 _ _ _ _ 5 1 _ _ _ _ 5 1 _ _ _ _ 0 2 _ _ _ _ 0 2 _ _ _ _ s n t p w h t d i w e s l u p e t i r w5 2 _ _ _ _ 0 4 _ _ _ _ 0 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 9 _ _ _ _ s n t r w e m i t y r e v o c e r e t i r w0 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 0 1 _ _ _ _ s n t z h w ) 3 ( z - h g i h n i t u p t u o o t e t i r w _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 5 3 _ _ _ _ 0 4 _ _ _ _ 0 4 _ _ _ _ 0 4s n t w d p a l r e v o e m i t e t i r w o t a t a d0 2 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 0 3 _ _ _ _ 5 3 _ _ _ _ 0 4 _ _ _ _ s n t h d ) 4 ( e m i t e t i r w m o r f d l o h a t a d0 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 0 1 _ _ _ _ s n t w o ) 4 , 3 ( e t i r w - f o - d n e m o r f e v i t c a t u p t u o0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n 5 1 l b t 9 8 0 3 5 1 a s 6 1 1 6 ) 1 ( 0 2 a s 6 1 1 6 0 2 a l 6 1 1 6 5 2 a s 6 1 1 6 5 2 a l 6 1 1 6 5 3 a s 6 1 1 6 ) 2 ( 5 3 a l 6 1 1 6 ) 2 ( l o b m y sr e t e m a r a p. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a mt i n u e l c y c e t i r w t c w e m i t e l c y c e t i r w5 1 _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 5 3 _ _ _ _ s n t w c e t i r w - f o - d n e o t t c e l e s p i h c3 1 _ _ _ _ 5 1 _ _ _ _ 7 1 _ _ _ _ 5 2 _ _ _ _ s n t w a e t i r w - f o - d n e o t d i l a v s s e r d d a4 1 _ _ _ _ 5 1 _ _ _ _ 7 1 _ _ _ _ 5 2 _ _ _ _ s n t s a e m i t p u - t e s s s e r d d a0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t p w h t d i w e s l u p e t i r w2 1 _ _ _ _ 2 1 _ _ _ _ 5 1 _ _ _ _ 0 2 _ _ _ _ s n t r w e m i t y r e v o c e r e t i r w0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t z h w ) 3 ( z - h g i h n i t u p t u o o t e t i r w _ _ _ _ 7 _ _ _ _ 8 _ _ _ _ 6 1 _ _ _ _ 0 2s n t w d p a l r e v o e m i t e t i r w o t a t a d2 1 _ _ _ _ 2 1 _ _ _ _ 3 1 _ _ _ _ 5 1 _ _ _ _ s n t h d ) 4 ( e m i t e t i r w m o r f d l o h a t a d0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t w o ) 4 , 3 ( e t i r w - f o - d n e m o r f e v i t c a t u p t u o0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n 4 1 l b t 9 8 0 3
6.42 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges 9 timing waveform of write cycle no. 1 ( we controlled timing) (1,2,5,7) timing waveform of write cycle no. 2 ( cs controlled timing) (1,2,3,5,7) notes: 1. we or cs must be high during all address transitions. 2. a write occurs during the overlap of a low cs and a low we . 3. t wr is measured from the earlier of cs or we going high to the end of the write cycle. 4. during this period, the i/o pins are in the output state and the input signals must not be applied. 5. if the cs low transition occurs simultaneously with or after the we low transition, the outputs remain in the high-impedance state. 6. transition is measured 500mv from steady state. 7. oe is continuously high. if oe is low during a we controlled write cycle, the write pulse width must be the larger of t wp or (t whz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the write pulse is the specified t wp . for a cs controlled write cycle, oe may be low with no degradation to t cw . address data out cs we data in t wc t aw 3089 drw 09 t as t whz (6) (4) t dw t dh (4) t ow t wr t chz (6) t wp (7) (6) previous data valid data valid data valid (3) , cs we data in t wc t aw t cw t wr (3) t dw t dh t as 3089 drw 10 data valid address ,
10 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges ordering information ? military ordering information ? commercial & industrial b td d 20 25 35 45 55 70 90 120 150 sa la military (-55 c to +125 c) compliant to mil-std-883, class b 300 mil cerdip (d24-1) 600 mil cerdip (d24-2) standard power low power 6116 device type xx power xxx speed x package x process/ temperature range 3089 drw 11 speed in nanoseconds blank i tp so 15* 20 25 sa la commercial (0 c to +70 c) industrial (-40 c to +85 c) 300 mil plastic dip (p24-1) 300 mil small outline ic, gull-wing bend (so24-2) standard power low power 6116 device type xx power xxx speed x package x process/ temperature range 3089 drw 12 speed in nanoseconds *available in commercial temperature range and standard power only. x g green blank 8 tube or tray tape and reel x
6.42 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges 11 datasheet document history 01/07/00 updated to new format pg. 1, 3, 4, 10 added industrial temperature range offerings pg. 9, 10 separated ordering information into military, commercial, and industrial temperature range offerings pg. 11 added datasheet document history 08/09/00 not recommended for new designs 02/01/01 removed "not recommended for new designs" 12/30/03 pg. 3,10 corrected industrial temp from -45c to -40c. 03/31/05 pg. 10 added "restricted hazardous substance device" to ordering information. 11/15/06 pg. 3 changed power limits for commercial and industrial on speed grades 25ns and 35ns. pg.4 changed power limits for commercial and industrial on speed grade 45ns. refer to pcn sr-0602-02. 04/26/11 pg.1,2,3,4,6,10 updated "restricted hazardous substance device" to "green". obsoleted 24-pin soj, 24-pin 600 mil and 35ns, 45ns for industrial & commercial. 05/01/13 pg. 1 description paragraph 4, package information. changed text to read "the idt6116sa/la is packaged in 24-pin 300mil plastic dip, 24-pin 600mil and 300mil ceramic dip, or 24-lead gull-wing soic providing high board-level packing densities". removed idt in reference to fabrication. pg. 3 updated dc elec chars (v cc = 5.0v 10%) table by adding industrial to the test conditions. updated dc elec chars (v cc = 5.0v 10%, v lc = 0.2v, v hc + v cc - 0.2v) table by removing the la power for the 15ns speed. pg. 10 removed footnote "*available in 300mil packaging only" from the military ordering information. the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: 6024 silver creek valley road 800-345-7015 or san jose, ca 95138 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: sramhelp@idt.com 408-284-4532

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